The present invention relates generally to integrated circuits (IC), and more particularly to the reduction of IC power noise generation through the utilization of dummy conductor configurations to increase the de-coupling capacitance within the IC.
Capacitors are a class of passive electronic elements useful for reduction of unwanted noise, for coupling of AC signals, and for constructing timing and phase shift networks. They are relatively bulky devices that store energy in electrostatic fields. The microscopic dimensions of today's ICs preclude the fabrication of more than a few hundred pico-farads of capacitance in an IC. Since conventional IC capacitor construction techniques limit an IC to a few hundred pico-farads, larger capacitors must reside off-chip (located on the associated printed circuit board). These off-chip capacitors are bulky and require significant PCB board space as well as additional material and processing costs. Also, due to their increased distance from the noise generating point within the IC, these off-chip capacitors are not as effective in IC noise reduction as the internal capacitors.
All of the capacitors used in ICs are of the sort called “parallel plate” capacitors, which consist of two conductive plates called “electrodes” attached to either side of a slab of insulating material typically known as dielectric. In the simple parallel-plate capacitor, the two electrodes are assumed to have the same dimensions and to reside directly opposite from one another. The value of the simple parallel-plate capacitor can be computed using the following approximate equation:C=0.0885 A(er)/twhere C is the capacitance in pico-farads, A is the area of either electrode in square microns (um2), t is the thickness of the dielectric in Angstroms, and er is a dimensionless constant called the “relative permittivity.”
er depends upon the nature of the dielectric and is sometimes called the “dielectric constant.” Consider a capacitor with a plate area of 0.1 mm2 constructed using a 200 A dry oxide film. If the dielectric permittivity is 4, then the capacitance will be approximately 180 pico-farads. This example explains why it is difficult to obtain internal capacitors of more than a few hundred pico-farads. As the IC geometries delve into the sub-micron level, internal IC capacitance will continue to decrease. Reducing the thickness of the dielectric increases the capacitance, but also increases the electric field across the dielectric. If the electric field increases beyond a certain point, a catastrophic short circuit of the capacitor is possible.
Current ICs have two typical capacitor types, either MOS capacitors or poly-poly capacitors. MOS capacitors consist of a thin layer of grown oxide formed on a silicon diffusion that serves as one of the electrodes. The other electrode consists of either metal or doped polysilicon. If the gate oxide is used to form a MOS capacitor, the resulting structure is called a “gate oxide capacitor”.
MOS capacitors have a number of disadvantages. These MOS capacitors are designed into the IC to provide as much de-coupling capacitance as possible to minimize IC internal noise generation. It utilizes unused areas within the IC. However, these devices require a large amount of chip area (typically 10-15% of chip area) that could have been used for additional circuitry or for a higher density of IC devices per wafer. Also, MOS devices have an inherently large device leakage current through the thinner gate oxide, especially for 90-nanometer and smaller IC geometries. This leakage current causes excessive power dissipation within the IC in both static and dynamic states. Also, because of the thin gate oxide layer in MOS devices, these devices are more susceptible to electro-static discharge (ESD) anomalies.
Poly-poly capacitors employ two polysilicon electrodes in combination with either an oxide or oxide-nitride-oxide (ONO) dielectric. Many CMOS and Bi-CMOS processes already incorporate multiple polysilicon layers, so poly-poly capacitors do not necessarily require any additional masking steps. Poly-poly capacitors normally reside over field oxide. Oxide steps should not intersect the structure because they can cause surface irregularities in the lower capacitor electrode.
Both the MOS capacitor and the poly-poly capacitor structures are considered thin-film capacitors. The microscopic dimensions of today's integrated circuits preclude the fabrication of more than a few hundred pico-farads of capacitance in an IC using either the MOS or poly-ploy capacitors.
Desirable in the art of IC design are additional circuits to reduce IC power system internal power noise generation by increasing the internal IC de-coupling capacitance between the IC power and ground.